Abstract— A novel half-pel full-search motion estimation VLSI architecture for H.264/AVC video encoders is presented in this paper. Based on the processing element arrays eliminating redundant data accesses and attaining 100 % utilization, the architecture can be implemented with low clock rate while having high processing throughput. Such an implementation is particularly suited to applications requiring real time operations with high compression efficiency and low power.

Index Terms— VLSI hardware architecture, Video coding, Fractional motion estimation, H.264 standard.

Chien-Min Ou and C. C. Liao are with the Department of Electronic Engineering, Chien Hsin University of Science and Technology, Zhongli City, Taoyuan 320 Taiwan (e-mail: {cmou, ccliao}@uch.edu.tw).

Cite: Chien-Min Ou and Chiung-Chou Liao, " Fractional Motion Estimation Hardware Circuits for H.264/ Advanced Video Coding," International Journal of e-Education, e-Business, e-Management and e-Learning vol. 4, no. 1, pp. 11-14, 2014.